RTL Design Engineer (Silicon Engineering)

RTL Design Engineer (Silicon Engineering) at SpaceX in Irvine, CA, United States. **What you'll do** - Design ASICs and/or FPGAs for Starlink projects using Verilog/SystemVerilog - Participate in the full ASIC/FPGA design lifecycle from architecture to validation - Engage in high-level architectural design for FPGA and ASICs - Collaborate with cross-functional teams to develop new technologies for the Starlink program **What they're looking for** - Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or Physics - 1+ years of experience in RTL Design using SystemVerilog, Verilog, or VHDL - Proficiency in Python for scripting - Experience with EDA tools such as HDL simulators **Details** - Location: Irvine, CA, United States

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